Computer Architecture (Fall 2022) | SNU Systems Software & Architecture Laboratory

News

   Please note the following information on the final exam:
   • Time: 15:30 - 16:45, December 13th.
   • Location: #302-105, #302-208, #302-209
   • Scope: Chap. 1.6, 1.9, 2.1-2.10, 2.13-2.14, 2.22, 4.1-4.4, 4.6-4.9, 4.15, 5.1-5.4, 5.8 (+ materials covered by lecture slides and project assignments)
   • Closed-book exam
   • Bring your student ID and wear a mask all the time during the exam. In case you are currently in self-quarantine, please let us know in advance.

(Posted Nov 30, 2022)

   The lecture on Nov. 24th will be conducted using Zoom. Please refer to the Zoom link posted in eTL.

(Posted Nov 23, 2022)

   Please note the following midterm exam logistics:
   • Time: 15:30 - 16:45, October 20th.
   • Location: #302-105 (max 80), #302-208 (max 38), #302-209 (max 38)
   • Scope: Chap. 1.1-1.5, 1.7-1.8, 2.1-2.4, 2.6-2.10, 2.13-2.14, 2.20, 2.22-2.23, 3.1-3.2, 3.5, 3.9-3.10 (+ materials covered by lecture slides and project assignments)
   • Closed-book exam
   • Bring your student ID and wear a mask all the time during the exam. In case you are currently in self-quarantine, please let us know in advance.

(Posted Oct 12, 2022)

Schedule

The following schedule is tentative and subject to change without notice.

Day Topic Reading
9/1 Course Overview
9/6 Introduction to Computer Architecture Chap. 1 (except 1.6, 1.9-10)
Reading: A New Golden Age for Computer Architecture
Lab. session #1
9/8
9/13 Integers Chap. 2.4, 3.1, 3.2
9/15
9/20 Floating Points Chap. 3.5, 3.9-3.10, 2.9
9/22
9/27
9/29 RISC-V Architecture I (Updated on 10/15) Chap. 2.1-2.3, 2.6
Reading: RISC-V Overview and ISA Design (HotChips ‘19)
10/4 Lab. session #2
10/6
10/11 RISC-V Architecture II (Updated on 10/13) Chap. 2.7-2.8, 2.10, 2.13-2.14
10/13
10/18 Machine-level Representation of Programs Chap. 2.5, 2.12, 2.19
10/20 Midterm Exam
10/25 Sequential Processor Chap. 4.1-4.4
10/27
11/1 Pipelining Chap. 4.6-4.7
11/3 Pipeline Hazards Chap. 4.8-4.9
Lab. session #3
11/8
11/10
11/15 Memory Hierarchy Chap. 5.1-5.2
11/17 Invited Talk: When two promising fabless startups who share the same design principle meet by chance in the era of post Moore’s law (by Dr. Eyee Hyun Nam, CEO/CTO and Co-founder of FADU Inc.)
11/22 Cache Chap. 5.3
11/24 Cache Optimization (Updated on 11/29) Chap. 5.4
11/29 Performance Chap. 1.6, 1.9, 2.13
Lab. session #4
12/1
12/6 Virtual Memory Chap. 5.7-5.8, 5.13, 5.16-5.17
12/8 Advanced Processor Architecture Chap. 4.10-4.11, 4.14-4.15
12/13 Final Exam

Credit: Most of slides for this lecture are based on materials provided by the textbook publisher.

Projects

For project submission and automatic grading, we are running a dedicated server at http://sys.snu.ac.kr. If you want to access the sys server outside of the SNU campus, please submit your IP through this Google Form.

Project #4: Extending a 5-stage Pipelined RISC-V Processor

The goal of this project is to understand how a pipelined processor works. In this project, you need to extend the existing 5-stage pipelined RISC-V simulator to support new instructions and a branch prediction scheme using the branch target buffer (BTB).

  • Project specification and skeleton code available here
  • Due date: 11:59PM, December 18 (Sunday).

Project #3: Image Resizing in the RISC-V Assembly Language

In this project, you will implement an image resizing program using the 32-bit RISC-V (RV32I) assembly language. An image file in the BMP format will be given as an input. The goal of this project is to give you an opportunity to practice the RISC-V assembly programming. In addition, this project introduces various RISC-V tools that help you compile and run your RISC-V programs.

  • Project specification and skeleton code available here
  • Due date: 11:59PM, November 20 (Sunday).

Project #2: FP Addition

The goal of this project is to get familiar with the IEEE 754 floating-point standard by implementing the addition of two floating-point numbers using integer arithmetic. Specificially, this project focuses on a variation of the 16-bit floating-point format, called SnuFloat16 (or SFP16 for short).

  • Project specification and skeleton code available here
  • Due date: 11:59PM, October 16 (Sunday).

Project #1: Simplified Image Compression

In this project, you need to perform a simplified image compression on the given grayscale image in memory. The purpose of this project is to make you familiar with the binary representation of integers and the bit-level operations supported in the C programming language. Another goal is to make your Linux or MacOS development environment ready and to get familiar with our project submission server.

  • Project specification and skeleton code available here
  • Due date: 11:59PM, September 18 (Sunday).

RISC-V Resources

Course Information

When 15:30 - 16:45 (Tuesday / Thursday)
Where Lecture room #302-105
Instructor Jin-Soo Kim
Professor, Dept. of Computer Science and Engineering, SNU
Language English
Course Description This course introduces the main components of a modern computer system including the instruction set, the processor, and the memory hierarchy. We cover techniques such as pipelining, caching, and virtual memory. In addition, this course gives a historical perspective on the evolution of computer systems and an overview of performance evaluation methodologies.
Textbook David A. Patterson and John L. Hennessy, Computer Organization and Design: RISC-V Edition, Second edition, Morgan Kaufmann, 2020.
(The First edition of this book is OK but not recommended.)
Reference Randal E. Bryant and David R. O’Hallaron, Computer Systems: A Programmer’s Perspective, 3rd Edition, Pearson Education Limited, 2016.
Prerequisites 4190.103A Programming Practice
M1522.000700 Logic Design
Basic knowledge of C & Python programming on Linux
Grading Exams: 60% (Midterm 25%, Final 35%)
Projects: 40%
* Grading policy is subject to change
Teaching Assistants Seongyeop Jeong (Head TA)
Jaehoon Shim
Ilkueon Kang
Wookje Han
Jinsol Park
(snucsl.ta AT gmail.com)