Computer Architecture (Fall 2021) | SNU Systems Software & Architecture Laboratory

News

   Please note the following final exam logistics:
   • Time: 14:00 - 15:15, December 14th.
   • Location: 302-105 (Max 60), 302-106 (Max 26), 302-107 (Max 26), and 302-209 (Max 32)
   • Scope: Chap. 1.6-1.9, 2.1-2.8, 2.13-2.14, 4.1-4.4, 4.6-4.9, 4.15-4.16 (4.1-4.8, 4.14-4.15 in 1st edition), 5.1-5.4, 5.7-5.8, 5.16-5.17 + materials covered by lecture slides and project assignments)
   • Closed-book exam
   • It is highly recommended to arrive at one of the lecture rooms in advance with your student ID. Also, please remember it is required for you to wear a face mask all the time during the exam. In case you are currently in self-quarantine or have COVID-19 symptoms, please let us know in advance.

(Posted Dec 8, 2021)

   The class on Nov. 25 will be held entirely online because the building 301 is temporarily closed during Nov. 24 ~ 26.

(Posted Nov 24, 2021)

   Please note that the lecture room for offline attendees has been changed to #301-203.

(Posted Nov 11, 2021)

Schedule

The following schedule is tentative and subject to change without notice.

Day Topic Reading
9/2 Course Overview (Online)
9/7 Introduction to Computer Architecture (Online) Chap. 1 (except 1.6, 1.9-10)
Reading: A New Golden Age for Computer Architecture
9/9 Integers (Online) Chap. 2.4, 3.1, 3.6
9/14
9/15 Lab. Session #1 @ 7:00pm (Online)
9/16 Floating Points (Online) Chap. 3.5, 3.9-3.10, 2.9
9/21 National Holiday
9/23
9/28 RISC-V Architecture I (Online) Chap. 2.1-2.3, 2.6
9/30
10/5
10/6 Lab. Session #2 @ 7:00pm (Online)
10/7 RISC-V Architecture II (Online) Chap. 2.7-2.8, 2.10, 2.13-2.14
10/8 Makeup Class @ 7:00pm (Online)
10/12 Machine-level Representation of Programs (Online) Chap. 2.5, 2.12, 2.19
10/14
10/19 Midterm Exam (Offline)
10/21 Sequential Processor (Hybrid) Chap. 4.1-4.4
10/26
10/28 Pipelining (Hybrid) Chap. 4.6-4.7
10/28 Lab. Session #3 @ 7:00pm (Online)
11/2 Pipeline Hazards (Hybrid) Chap. 4.8-4.9
11/4
11/9
11/11 Memory Hierarchy (Hybrid) Chap. 5.1-5.2
11/16 Cache (Hybrid) Chap. 5.3
11/18 Cache Optimization (Hybrid) Chap. 5.4
11/23
11/25 Performance (Online) Chap. 1.6, 1.9, 2.13
11/26 Lab. Session #4 @ 4:00pm (Online)
11/30
12/2 Virtual Memory (Hybrid) Chap. 5.7-5.8, 5.13, 5.16-5.17
12/7
12/9 Advanced Processor Architecture (Hybrid) Chap. 4.10-4.11, 4.14-4.15
12/14 Final Exam (Offline)

Credit: Most of slides for this lecture are based on materials provided by the textbook publisher.

Projects

For project submission and automatic grading, we are running a dedicated server at http://sys.snu.ac.kr. If you want to access the sys server outside of the SNU campus, please send a mail to the TAs at snucsl.ta AT gmail.

Project #4: A 6-stage Pipelined RISC-V Simulator

The goal of this project is to understand how a pipelined processor works. You need to build a 6-stage pipelined RISC-V simulator called snurisc6 in Python that supports the most of RV32I base instruction set.

  • Project specification and skeleton code available here
  • Due date: 11:59PM, December 18 (Saturday).

Project #3: Image Convolution in the RISC-V Assembly Language

In this project, you will implement an image convolution routine using the 32-bit RISC-V (RV32I) assembly language. An image file in the BMP format will be given as an input. The goal of this project is to give you an opportunity to practice the RISC-V assembly programming. In addition, this project introduces various RISC-V tools that help you compile and run your RISC-V programs.

  • Project specification and skeleton code available here
  • Due date: 11:59PM, November 14 (Sunday).

Project #2: FP10 Representation

The goal of this project is to get familiar with the IEEE 754 floating-point standard by implementing a 10-bit floating-point representation (fp10 for short).

  • Project specification and skeleton code available here
  • Due date: 11:59PM, October 17 (Sunday).

Project #1: Run-length Encoding

In this project, you need to perform a variant of run-length encoding to the given array of bytes in memory. The purpose of this project is to make you familiar with the binary representations of strings/integers and the logical operations supported in the C programming language. Another goal is to make your Linux or MacOS development environment ready and to get familiar with our project submission server.

  • Project specification and skeleton code available here
  • Due date: 11:59PM, September 26 (Sunday).

RISC-V Resources

Course Information

When 14:00 - 15:15 (Tuesday / Thursday)
Where Online lectures using Zoom
Lecture room #302-208 #301-203 (Hybrid lectures after midterm)
Instructor Jin-Soo Kim
Professor, Dept. of Computer Science and Engineering, SNU
Language English
Course Description This course introduces the main components of a modern computer system including the instruction set, the processor, and the memory hierarchy. We cover techniques such as pipelining, caching, and virtual memory. In addition, this course gives a historical perspective on the evolution of computer systems and an overview of performance evaluation methodologies.
Textbook David A. Patterson and John L. Hennessy, Computer Organization and Design: RISC-V Edition, Second edition, Morgan Kaufmann, 2020.
(The First edition of this book is also OK.)
Reference Randal E. Bryant and David R. O’Hallaron, Computer Systems: A Programmer’s Perspective, 3rd Edition, Pearson Education Limited, 2016.
Prerequisites 4190.103A Programming Practice
M1522.000700 Logic Design
Basic knowledge of C & Python programming on Linux
Grading Exams: 60% (Midterm 25%, Final 35%)
Projects: 40%
* Grading policy is subject to change
Teaching Assistants Jaehoon Shim (mattjs AT snu)
Ikjoon Son (ikjoon.son AT snu)
Seongyeop Jeong (seongyeop.jeong AT snu)