The following schedule is tentative and subject to change without notice.

Credit: Most of slides for this lecture are based on materials provided by the textbook publisher.

For project submission and automatic grading, we are running a dedicated server at http://sys.snu.ac.kr. If you want to access the sys server outside of the SNU campus, please send a mail to the TAs at snucsl.ta AT gmail.

The RISC-V Instruction Set Manual

• Volume I: Unprivileged ISA (version 20191213)

Project #4: A 6-stage Pipelined RISC-V Simulator

The goal of this project is to understand how a pipelined processor works. You need to build a 6-stage pipelined RISC-V simulator called snurisc6 in Python that supports the most of RV32I base instruction set.

• Project specification and skeleton code available here
• Due date: 11:59PM, December 16 (Wednesday)

Project #3: RISC-V Assembly Programming

The goal of this project is to give you an opportunity to practice RISC-V assembly programming. In addition, this project introduces various RISC-V tools that help you compile and run your RISC-V programs.

• Project specification and skeleton code available here
• Due date: 11:59PM, November 8 (Sunday).

Project #2: FP12 (12-bit Floating Point) Representation

The goal of this project is to get familiar with the IEEE 754 floating-point standard by implementing a 12-bit floating-point representation (fp12 for short).

• Project specification and skeleton code available here
• Due date: 11:59PM, October 11 (Sunday).

Project #1: Compressing Data with Huffman Coding

This project demonstrates how we can compress data using a simplified Huffman coding. The purpose of this project is to make you familiar with the binary representations of strings/integers and the logical operations supported in the C programming language. Another goal is to make your Linux or MacOS development environment ready and to get familiar with our project submission server.

• Project specification and skeleton code available here
• Due date: 11:59PM, September 20 (Sunday).